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| CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V FLEx18TM 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM Features * True dual-ported memory cells that allow simultaneous access of the same memory location * Synchronous pipelined operation * Organization of 1 Mbit, 2 Mbits, 4 Mbits and 9 Mbits devices * Pipelined output mode allows fast operation * 0.18-micron CMOS for optimum speed and power * High-speed clock to data access * 3.3V low power -- Active as low as 225 mA (typ) -- Standby as low as 55 mA (typ) * Mailbox function for message passing * Global master reset * Separate byte enables on both ports * Commercial and industrial temperature ranges * IEEE 1149.1-compatible JTAG boundary scan * 256-ball FBGA (1 mm pitch) * Counter wrap-around control -- Internal mask register controls counter wrap-around -- Counter-interrupt flags to indicate wrap-around -- Memory block retransmit operation * Counter readback on address lines * Mask register readback on address lines * Dual Chip Enables on both ports for easy depth expansion * Seamless migration to next-generation dual-port family Functional Description The FLEx18TM family includes 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time. During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally (more details to follow). The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (CNTINT) flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset (MRST). The CYD09S18V device in this family has limited features. Please see Address Counter and Mask Register Operations on page 5 for details. Seamless Migration to Next Generation Dual Port Family Cypress offers a migration path for all devices in this family to the next-generation devices in the Dual-Port family with a compatible footprint. Please contact Cypress Sales for more details. Table 1. Product Selection Guide Density Part Number Max. Speed (MHz) Max. Access Time - Clock to Data (ns) Typical operating current (mA) Package 1 Mbit (64K x 18) CYD01S18V 167 4.0 225 2 Mbit (128K x 18) CYD02S18V 167 4.0 225 4 Mbit (256K x 18) CYD04S18V 167 4.0 225 9 Mbit (512K x 18) CYD09S18V 133 4.7 270 256FBGA 256FBGA 256FBGA 256FBGA (17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) Cypress Semiconductor Corporation Document #: 38-06077 Rev. *C * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised May 5, 2005 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Logic Block Diagram[1] FTSELL CONFIG Block PORTSTD(1:0)L CONFIG Block PORTSTD(1:0)R FTSELR DQ (17:0)L BE (1:0)L CE0L CE1L OEL R/WL IO Control IO Control DQ (17:0)R BE (1:0)R CE0R CE1R OER R/WR Dual Ported Array BUSYL Arbitration Logic BUSYR A (18:0)L CNT/MSKL ADSL CNTENL CNTRSTL RETL CNTINTL CL WRPL Address & Counter Logic Address & Counter Logic A (18:0)R CNT/MSKR ADSR CNTENR CNTRSTR RETR CNTINTR CR WRPR Mailboxes INTL INTR JTAG TRST TMS TDI TDO TCK READYL LowSPDL RESET LOGIC MRST READYR LowSPDR Note: 1. CYD01S18V has 16 address bits, CYD02S18V has 17 address bits, CY04S18V has 18 address bits and CYD09S18V has 19 address bits. Document #: 38-06077 Rev. *C Page 2 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Pin Configurations 256-ball BGA Top View CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V 1 A B C D E F G H J K L M N P R T NC 2 NC 3 NC 4 DQ17L 5 DQ16L 6 DQ13L 7 DQ12L 8 DQ9L 9 DQ9R 10 DQ12R 11 DQ13R 12 DQ16R 13 DQ17R 14 NC 15 NC 16 NC NC NC NC NC DQ15L NC [2,5] FTSELL [2,3] DQ14L NC [2,5] LowSPDL [2,4] DQ11L REVL [2,4] DQ10L TRST [2,5] VTTL DQ10R DQ11R NC [2,5] DQ14R NC [2,5] LowSPDR [2,4] DQ15R NC [2,5] FTSELR [2,3] NC NC NC NC NC NC RETL [2,3] INTL VREFL [2,4] CE1L [9] MRST INTR VREFR [2,4] CE1R [9] RETR [2,3] NC NC A0L A1L WRPL [2,3] VSS VTTL VSS WRPR [2,3] CE0R [10] A1R A0R A2L A3L CE0L [10] CNTINTL [11] VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR A3R A2R A4L A5L NC VDDIOL REVL [2,3] VSS VSS VSS VSS VSS VSS VDDIOR NC CNTINTR [11] A5R A4R A6L A7L BUSYL [2,5] NC VSS VSS VSS VSS VSS VSS VDDIOR NC BUSYR [2,5] CR A7R A6R A8L A9L CL VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL A9R A8R A10L A11L VSS PortSTD1L [2,4] VCORE VSS VSS VSS VSS VSS VSS VCORE PortSTD1R [2,4] VSS A11R A10R A12L A13L OEL ADSL [10] BE1L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE1R BE0R OER ADSR [10] A13R A12R A14L A16L [6] A18L [8] A15L A17L [7] BE0L REVL [2,4] VREFL VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR A15R A17R [7] A14R A16R [6] A18R [8] RWL CNT/ MSKL [9] CNTENL [10] VDDIOL VDDIOL VDDIOL REVL [2,3] VCORE VCORE VDDIOR REVR [2,3] VDDIOR VDDIOR REVR [2,4] VREFR RWR CNT/ MSKR [9] CNTENR [10] NC [2,4] PortSTD0L [2,4] READYL [2,5] VTTL VTTL READYR [2,5] PortSTD0R [2,4] [2,4] NC NC NC CNTRSTL [9] NC [2,5] DQ6L NC [2,5] DQ5L TCK TMS TDO TDI NC [2,5] DQ5R NC [2,5] DQ6R CNTRSTR [9] NC NC NC NC NC NC DQ2L DQ1L DQ1R DQ2R NC NC NC NC NC NC NC DQ8L DQ7L DQ4L DQ3L DQ0L DQ0R DQ3R DQ4R DQ7R DQ8R NC NC NC Notes: 2. This ball will represent a next generation FLEx18-E Dual-Port feature. For more information about this feature, contact Cypress Sales. 3. Connect this ball to VDDIO. For more information about this next generation FLEx18-E Dual-Port feature contact Cypress Sales. 4. Connect this ball to VSS. For more information about this next generation FLEx18-E Dual-Port feature, contact Cypress Sales. 5. Leave this ball unconnected. For more information about this feature, contact Cypress Sales. 6. Leave this ball unconnected for a 64K x 18. 7. Leave this ball unconnected for a 128K x 18 and 64K x 18. 8. Leave this ball unconnected for a 256K x 18, 128K x 18 and 64K x 18. 9. These balls are not applicable for CYD09S18V device. They need to be tied to VDDIO. 10. These balls are not applicable for CYD09S18V device. They need to be tied to VSS. 11. These balls are not applicable for CYD09S18V device. They need to be no connected. Document #: 38-06077 Rev. *C Page 3 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Pin Definitions Left Port A0L-A18L BE0L-BE1L BUSYL[2,5] CL CE0L [10] Right Port A0R-A18R BE0R-BE1R BUSYR[2,5] CR CE0R [10] Description Address Inputs. Byte Enable Inputs. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. Port Busy Output. When the collision is detected, a BUSY is asserted. Input Clock Signal. Active Low Chip Enable Input. Active High Chip Enable Input. Data Bus Input/Output. Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data pins during Read operations. Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two memory locations can be used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. Port Low Speed Select Input. When operating at less than 100 MHz, the LowSPD disables the port DLL. Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to read from the dual-port memory array. Port Ready Output. This signal will be asserted when a port is ready for normal operation. Port Counter/Mask Select Input. Counter control input. Port Counter Address Load Strobe Input. Counter control input. Port Counter Enable Input. Counter control input. Port Counter Reset Input. Counter control input. Port Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter is incremented to all "1s". Port Counter Wrap Input. After the burst counter reaches the maximum count, if WRP is low, the unmasked counter bits will be set to 0. If high, the counter will be loaded with the value stored in the mirror register. Port Counter Retransmit Input. Counter control input. Flow-Through Mode Select Input. Port External High-Speed IO Reference Input. Port IO Power Supply. Reserved pins for future features. Master Reset Input. MRST is an asynchronous input signal and affects both ports. A master reset operation is required at power-up. JTAG Reset Input. JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. JTAG Test Clock Input. JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. CE1L[9] DQ0L-DQ17L OEL INTL CE1R[9] DQ0R-DQ17R OER INTR LowSPDL[2,4] LowSPDR[2,4] PORTSTD[1:0]L[2,4] PORTSTD[1:0]R[2,4] Port Address/Control/Data I/O Standard Select Input. R/WL READYL[2,5] CNT/MSKL[9] ADSL[10] CNTENL[10] CNTRSTL[9] CNTINTL[11] WRPL[2,3] RETL[2,3] FTSELL VREFL [2,3] [2,4] R/WR READYR[2,5] CNT/MSKR[9] ADSR[10] CNTENR[10] CNTRSTR[9] CNTINTR[11] WRPR[2,3] RETR[2,3] FTSELR [2,3] VREFR[2,4] VDDIOR REVR[2,4] MRST TRST[2,5] TMS TDI TCK TDO VDDIOL REVL[2,4] Document #: 38-06077 Rev. *C Page 4 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Pin Definitions (continued) Left Port VSS VCORE[12] VTTL Right Port Ground Inputs. Core Power Supply. LVTTL Power Supply. Description Master Reset The FLEx18 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchronously to the clocks. The MRST initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). The MRST also forces the Mailbox Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH. The MRST must be performed on the FLEx18 family devices after power-up. Address Counter and Mask Register Operations This section describes the features only apply to 1-Mbit, 2-Mbit, and 4-Mbit devices. It does not apply to a 9-Mbit device. Each port of these devices has a programmable burst address counter. The burst counter contains three registers: a counter register, a mask register, and a mirror register.[17] The counter register contains the address used to access the RAM array. It is changed only by the Counter Load, Increment, Counter Reset, and by master reset (MRST) operations. The mask register value affects the Increment and Counter Reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is changed only by the Mask Load and Mask Reset operations, and by the MRST. The mask register defines the counting range of the counter register. It divides the counter register into two regions: zero or more "0s" in the most significant bits define the masked region, one or more "1s" in the least significant bits define the unmasked region. Bit 0 may also be "0," masking the least significant counter bit and causing the counter to increment by two instead of one. The mirror register is used to reload the counter register on increment operations (see "retransmit," below). It always contains the value last loaded into the counter register, and is changed only by the Counter Load, and Counter Reset operations, and by the MRST. Table 3 summarizes the operation of these registers and the required input control signals. The MRST control signal is asynchronous. All the other control signals in Table 3 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the port's CLK. All these counter and mask operations are independent of the port's chip enable inputs (CE0 and CE1). Mailbox Interrupts The upper two memory locations may be used for message passing and permit communications between ports. Table shows the interrupt operation for both ports of CYD09S18V. The highest memory location, 7FFFF is the mailbox for the right port and 7FFFE is the mailbox for the left port. Table shows that in order to set the INTR flag, a Write operation by the left port to address 7FFFF will assert INTR LOW. At least one byte has to be active for a Write to generate an interrupt. A valid Read of the 7FFFF location by the right port will reset INTR HIGH. At least one byte has to be active in order for a Read to reset the interrupt. When one port Writes to the other port's mailbox, the INT of the port that the mailbox belongs to is asserted LOW. The INT is reset when the owner (port) of the mailbox Reads the contents of the mailbox. The interrupt flag is set in a flow-thru mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-thru mode (i.e., it follows the clock edge of the reading port). Each port can read the other port's mailbox without resetting the interrupt. And each port can write to its own mailbox without setting the interrupt. If an application does not require message passing, INT pins should be left open. Table 2. Interrupt Operation Example [1, 13, 14, 15, 16] Left Port Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag R/WL L X X H CEL L X X L A0L-18L 7FFFF X X 7FFFE INTL X X L H R/WR X H L X CER X L L X Right Port A0R-18R X 7FFFF 7FFFE X INTR L H X X Notes: 12. This family of Dual-Ports does not use VCORE, and these pins are internally NC. The next generation Dual-Port family, the FLEx18-ETM, will use VCORE of 1.5V or 1.8V. Please contact local Cypress FAE for more information. 13. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge. 14. OE is "Don't Care" for mailbox operation. 15. At least one of BE0, BE1 must be LOW. 16. A18x is a NC for CYD04S18V, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CYD02S18V, therefore the Interrupt addresses are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CYD01S18V, therefore the Interrupt Addresses are FFFF and FFFE. 17. This section describes the CYD04S18V, CYD02S18V, CYD01S18V 18, 17, and 16 address bits. Document #: 38-06077 Rev. *C Page 5 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port) [18, 19] CLK X MRST L H H H H H H H H H CNT/MSK X H H H H H L L L L CNTRST X L H H H H L H H H ADS X X L L H H X L L H CNTEN X X L H L H X L H X Operation Master Reset Counter Reset Counter Load Description Reset address counter to all 0s and mask register to all 1s. Reset counter unmasked portion to all 0s. Load counter with external address value presented on address lines. Counter Readback Read out counter internal value on address lines. Counter Increment Internally increment address counter value. Counter Hold Mask Reset Mask Load Mask Readback Reserved Constantly hold the address value for multiple clock cycles. Reset mask register to all 1s. Load mask register with value presented on the address lines. Read out mask register value on address lines. Operation undefined Counter enable (CNTEN) inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast, interleaved memory applications. A port's burst counter is loaded when the port's address strobe (ADS) and CNTEN signals are LOW. When the port's CNTEN is asserted and the ADS is deasserted, the address counter will increment on each LOW to HIGH transition of that port's clock signal. This will Read/Write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array, and will loop back to the start. Counter reset (CNTRST) is used to reset the unmasked portion of the burst counter to 0s. A counter-mask register is used to control the counter wrap. Counter Reset Operation All unmasked bits of the counter and mirror registers are reset to "0." All masked bits remain unchanged. A Mask Reset followed by a Counter Reset will reset the counter and mirror registers to 00000, as will master reset (MRST). Counter Load Operation The address counter and mirror registers are both loaded with the address value presented at the address lines. Counter Increment Operation Once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addressing the entire memory array. Only the unmasked bits of the counter register are incremented. The corresponding bit in the mask register must be a "1" for a counter bit to change. The counter register is incremented by 1 if the least significant bit is unmasked, and by 2 if it is masked. If all unmasked bits are "1," the next increment will wrap the counter back to the initially loaded value. If an Increment results in all the unmasked bits of the counter being "1s," a counter interrupt flag (CNTINT) is asserted. The next Increment will return the counter register to its initial value, which was stored in the mirror register. The counter address can instead be forced to loop to 00000 by externally connecting CNTINT to CNTRST.[20] An increment that results in one or more of the unmasked bits of the counter being "0" will deassert the counter interrupt flag. The example in Figure 2 shows the counter mask register loaded with a mask value of 0003Fh unmasking the first 6 bits with bit "0" as the LSB and bit "16" as the MSB. The maximum value the mask register can be loaded with is 3FFFFh. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of 8h. The base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. The counter address will start at address 8h. The counter will increment its internal address value till it reaches the mask register value of 3Fh. The counter wraps around the memory block to location 8h at the next count. CNTINT is issued when the counter reaches its maximum value. Counter Hold Operation The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. Such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. Notes: 18. "X" = "Don't Care," "H" = HIGH, "L" = LOW. 19. Counter operation and mask register operation is independent of chip enables. 20. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together. Document #: 38-06077 Rev. *C Page 6 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Counter Interrupt The counter interrupt (CNTINT) is asserted LOW when an increment operation results in the unmasked portion of the counter register being all "1s." It is deasserted HIGH when an Increment operation results in any other value. It is also deasserted by Counter Reset, Counter Load, Mask Reset and Mask Load operations, and by MRST. Counter Readback Operation The internal value of the counter register can be read out on the address lines. Readback is pipelined; the address will be valid tCA2 after the next rising edge of the port's clock. If address readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. Retransmit Retransmit is a feature that allows the Read of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal "mirror register" is used to store the initially loaded address counter value. When the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this "mirror register." If the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the "mirror register." Thus, the repeated access of the same data is allowed without the need for any external logic. Mask Reset Operation The mask register is reset to all "1s," which unmasks every bit of the counter. Master reset (MRST) also resets the mask register to all "1s." Mask Load Operation The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment operations. Permitted values are of the form 2n - 1 or 2n - 2. From the most significant bit to the least significant bit, permitted values have zero or more "0s," one or more "1s," or one "0." Thus 3FFFF, 003FE, and 00001 are permitted values, but 3F0FF, 003FC, and 00000 are not. Mask Readback Operation The internal value of the mask register can be read out on the address lines. Readback is pipelined; the address will be valid tCM2 after the next rising edge of the port's clock. If mask readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. Counting by Two When the least significant bit of the mask register is "0," the counter increments by two. This may be used to connect the x18 devices as a 36-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 36-bit data in even memory locations, and the other half in odd memory locations. Document #: 38-06077 Rev. *C Page 7 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V CNT/MSK CNTEN ADS CNTRST MRST Decode Logic Bidirectional Address Lines Mask Register Counter/ Address Register Address Decode RAM Array CLK From Address Lines 17 Mirror Load/Increment Counter 1 1 0 0 To Readback and Address Decode From Mask Register 17 Increment Logic Wrap 17 From Mask From Counter 17 17 +1 1 +2 0 17 Bit 0 Wrap Detect Wrap 1 0 17 To Counter Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1] Document #: 38-06077 Rev. *C Page 8 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Example: Load Counter-Mask Register = 3F CNTINT H 00 216 215 0s 011 1 1 1 1 Mask Register bit-0 26 25 24 23 22 21 20 Masked Address Unmasked Address Load Address Counter = 8 H XX 216 215 Xs X00 1 0 0 0 Address Counter bit-0 1 26 25 24 23 22 21 20 Xs X11 1 11 Max Address Register L XX 216 215 26 25 24 23 22 21 20 Xs X0 0 1 00 0 Max + 1 Address Register H XX 216 215 26 25 24 23 22 21 20 Figure 2. Programmable Counter-Mask Register Operation[1, 21] IEEE 1149.1 Serial Boundary Scan (JTAG)[22] The FLEx18 family devices incorporate an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant TAPs. The TAP operates using JEDEC-standard 3.3V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the devices, and may be performed while the device is operating. An MRST must be performed on the devices after power-up. Performing a Pause/Restart When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan chain will output the next bit in the chain twice. For example, if the value expected from the chain is 1010101, the device will output a 11010101. This extra bit will cause some testers to report an erroneous failure for the devices in a scan test. Therefore the tester should be configured to never enter the PAUSE-DR state. Boundary Scan Hierarchy for 9-Mbit Device Internally, the CYD09S18V have two DIEs. Each DIE contains all the circuitry required to support boundary scan testing. The circuitry includes the TAP, TAP controller, instruction register, and data registers. The circuity and operation of the DIE boundary scan are described in detail below. The scan chain of each DIEs are connected serially to form the scan chain of the CYD09S18V as shown in Figure 3. TMS and TCK are connected in parallel to each DIE to drive all TAP controllers in unison. In many cases, each DIE will be supplied with the same instruction. In other cases, it might be useful to supply different instructions to each DIE. One example would be testing the device ID of one DIE while bypassing the others. Each pin of the FLEx18 9-Mb device is typically connected to two DIEs. For connectivity testing with the EXTEST instruction, it is desirable to check the internal connections between DIEs as well as the external connections to the package. This can be accomplished by merging the netlist of the devices with the netlist of the user's circuit board. To facilitate boundary scan testing of the devices, Cypress provides the BSDL file for each DIE, the internal netlist of the device, and a description of the device scan chain. The user can use these materials to easily integrate the devices into the board's boundary scan environment. Further information can be found in the Cypress application note Using JTAG Boundary Scan For System In a Package (SIP) Dual-Port SRAMs. Notes: 21. The "X" in this diagram represents the counter upper bits. 22. Boundary scan is IEEE 1149.1-compatible. See "Performing a Pause/Restart" for deviation from strict 1149.1 compliance. Document #: 38-06077 Rev. *C Page 9 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V TDO TDO D2 TDI TDO D1 TDI TDI Figure 3. Scan Chain for 9-Mbit Device Table 4. Identification Register Definitions Instruction Field Revision Number (31:28) Cypress Device ID (27:12) 0h C090h C091h C093h Cypress JEDEC ID (11:1) ID Register Presence (0) Table 5. Scan Register Sizes Register Name Instruction Bypass Identification Boundary Scan Table 6. Instruction Identification Codes Instruction EXTEST BYPASS IDCODE HIGHZ CLAMP SAMPLE/PRELOAD NBSRST RESERVED 0000 1111 1011 0111 0100 1000 1100 All other codes Code Description Captures the Input/Output ring contents. Places the BSR between the TDI and TDO. Places the BYR between TDI and TDO. Loads the IDR with the vendor ID code and places the register between TDI and TDO. Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state. Controls boundary to 1/0. Places BYR between TDI and TDO. Captures the input/output ring contents. Places BSR between TDI and TDO. Resets the non-boundary scan logic. Places BYR between TDI and TDO. Other combinations are reserved. Do not use other than the above. Bit Size 4 1 32 n[23] 034h 1 Value Reserved for version number. Defines Cypress part number for CYD04S18V and CYD09S18V DIE Defines Cypress part number for CYD02S18V Defines Cypress part number for CYD01S18V Allows unique identification of the DP family device vendor. Indicates the presence of an ID register. Description Note: 23. See details in the device BSDL file. Document #: 38-06077 Rev. *C Page 10 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Maximum Ratings[24] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State...........................-0.5V to VDD +0.5V DC Input Voltage...............................-0.5V to VDD + 0.5V[25] Range Commercial Industrial Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2000V (JEDEC JESD22-A114-2000B) Latch-up Current..................................................... > 200 mA Operating Range Ambient Temperature 0C to +70C VDDIO/VTTL VCORE[12] 3.3V165 mV 1.8V100 mV -40C to +85C 3.3V165 mV 1.8V100 mV Electrical Characteristics Over the Operating Range -167 Parameter VOH VOL VIH VIL IOZ IIX1 IIX2 ICC Description Output LOW Voltage (VDD = Min., IOL= +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Input Leakage Current TDI, TMS, MRST Operating Current for (VDD = Max.,IOUT = 0 mA), Outputs Disabled [26] -133 2.4 0.4 0.4 2.0 0.8 0.8 -10 -10 -1.0 225 10 10 0.1 300 -10 -10 -1.0 10 10 0.1 2.0 2.4 -100 V 0.4 0.8 10 10 0.1 V V V A A mA mA Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Output HIGH Voltage (VDD = Min., IOH= -4.0 mA) 2.4 2.0 -10 -1.0 225 Input Leakage Current Except TDI, TMS, MRST -10 CYD01S18V CYD02S18V CYD04S18V CYD09S18V 300 270 90 160 55 160 115 210 75 210 90 160 55 160 400 115 210 75 210 75 200 310 mA mA mA mA mA ISB1 Standby Current (Both Ports TTL Level) CEL and CER VIH, f = fMAX Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL and CER VDD - 0.2V, f = 0 Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX Operating Current (VDDIO = Max, Iout=0mA,f=0) Outputs Disabled CYD09S18V ISB2[26] ISB3[26] ISB4[26] ISB5 ICORE[12] 75 mA Core Operating Current for (VDD = Max., IOUT = 0 mA), Outputs Disabled 0 0 0 0 0 0 mA Capacitance[27] Part Number CYD01S18V CYD02S18V CYD04S18V CYD09S18V Parameter CIN COUT CIN Description Input Capacitance Output Capacitance Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V Max. 13 10 22 20 Unit pF pF pF pF COUT Output Capacitance Notes: 24. The voltage on any input or I/O pin can not exceed the power pin during power-up. 25. Pulse width < 20 ns. 26. ISB1, ISB2, ISB3 and ISB4 are not applicable for CYD09S18V because it can not be powered down by using chip enable pins. 27. COUT also references CI/O Document #: 38-06077 Rev. *C Page 11 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V AC Test Load and Waveforms 3.3V Z0 = 50 OUTPUT C = 10 pF VTH = 1.5V OUTPUT C = 5 pF R2 = 435 R = 50 R1 = 590 (a) Normal Load (Load 1) 3.0V 90% ALL INPUT PULSES Vss < 2 ns 10% (b) Three-state Delay (Load 2) 90% 10% < 2 ns Switching Characteristics Over the Operating Range -167 CYD01S18V CYD02S18V CYD04S18V Parameter fMAX2 tCYC2 tCH2 tCL2 tR[28] tF[28] tSA tHA tSB tHB tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tSCM tHCM tOE tOLZ[29, 30] Description Maximum Operating Frequency Clock Cycle Time Clock HIGH Time Clock LOW Time Clock Rise Time Clock Fall Time Address Set-up Time Address Hold Time Byte Select Set-up Time Byte Select Hold Time Chip Enable Set-up Time Chip Enable Hold Time R/W Set-up Time R/W Hold Time Input Data Set-up Time Input Data Hold Time ADS Set-up Time ADS Hold Time CNTEN Set-up Time CNTEN Hold Time CNTRST Set-up Time CNTRST Hold Time CNT/MSK Set-up Time CNT/MSK Hold Time Output Enable to Data Valid OE to Low Z 0 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 4.0 0 6.0 2.7 2.7 2.0 2.0 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 4.4 0 Min. Max. 167 7.5 3.0 3.0 2.0 2.0 2.5 0.6 2.5 0.6 NA NA 2.5 0.6 2.5 0.6 NA NA NA NA NA NA NA NA 4.7 0 -133 CYD01S18V CYD02S18V CYD04S18V Min. Max. 133 7.5 3.0 3.0 2.0 2.0 3.0 0.6 3.0 0.6 NA NA 3.0 0.6 3.0 0.6 NA NA NA NA NA NA NA NA 5.0 -100 CYD09S18V Min. Max. 133 CYD09S18V Min. 10 4.0 4.0 3.0 3.0 Max. 100 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 28. Except JTAG signals (tr and tf < 10 ns [max.]). 29. This parameter is guaranteed by design, but it is not production tested. 30. Test conditions used are Load 2. Document #: 38-06077 Rev. *C Page 12 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Switching Characteristics Over the Operating Range (continued) -167 CYD01S18V CYD02S18V CYD04S18V Parameter tOHZ[29, 30] tCD2 tCA2 tCM2 tDC tCKHZ[29,30] tCKLZ[29, 30] tSINT tRINT tSCINT tRCINT tCCS tRS tRS tRSR tRSF tRSINT Description OE to High Z Clock to Data Valid Clock to Counter Address Valid Clock to Mask Register Readback Valid Data Output Hold After Clock HIGH Clock HIGH to Output High Z Clock HIGH to Output Low Z Clock to INT Set Time Clock to INT Reset Time Clock to CNTINT Set Time Clock to CNTINT Reset time Clock to Clock Skew Master Reset Pulse Width Master Reset Set-up Time Master Reset Recovery Time Master Reset to Outputs Inactive Master Reset to Counter and Mailbox Interrupt Flag Reset Time 1.0 0 1.0 0.5 0.5 0.5 0.5 5.2 5.0 6.0 5.0 10.0 10.0 4.0 4.0 6.7 6.7 5.0 5.0 Min. 0 Max. 4.0 4.0 4.0 4.0 1.0 0 1.0 0.5 0.5 0.5 0.5 6.0 5.0 6.0 5.0 10.0 10.0 4.4 4.4 7.5 7.5 5.7 5.7 -133 CYD01S18V CYD02S18V CYD04S18V Min. 0 Max. 4.4 4.4 4.4 4.4 1.0 0 1.0 0.5 0.5 NA NA 6.0 5.0 6.0 5.0 10.0 NA 4.7 4.7 7.5 7.5 NA NA -100 CYD09S18V Min. 0 Max. 4.7 4.7 NA NA CYD09S18V Min. 0 Max. 5.0 5.0 NA NA 1.0 0 1.0 0.5 0.5 NA NA 8.0 5.0 8.5 5.0 10.0 NA 5.0 5.0 10 10 NA NA Unit ns ns ns ns ns ns ns ns ns ns ns ns cycles ns cycles ns ns Port to Port Delays Master Reset Timing JTAG Timing and Switching Waveforms CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Parameter fJTAG tTCYC tTH tTL tTMSS tTMSH tTDIS tTDIH tTDOV tTDOX TCK Clock Cycle Time TCK Clock HIGH Time TCK Clock LOW Time TMS Set-up to TCK Clock Rise TMS Hold After TCK Clock Rise TDI Set-up to TCK Clock Rise TDI Hold After TCK Clock Rise TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 Description Maximum JTAG TAP Controller Frequency 100 40 40 10 10 10 10 30 Min. Max. 10 Unit MHz ns ns ns ns ns ns ns ns ns Document #: 38-06077 Rev. *C Page 13 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V tTH tTL Test Clock TCK Test Mode Select TMS tTMSS tTCYC tTMSH tTDIS Test Data-In TDI Test Data-Out TDO tTDIH tTDOX tTDOV Switching Waveforms Master Reset MRST ALL ADDRESS/ DATA LINES ALL OTHER INPUTS TMS tRSINT CNTINT INT TDO tRSF tRSS tRSR ACTIVE tRS INACTIVE Document #: 38-06077 Rev. *C Page 14 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Switching Waveforms (continued) Read Cycle[13, 31, 32, 33, 34] tCH2 CLK tCYC2 tCL2 CE tSC tSB BE0-BE1 tHC tHB tSC tHC R/W tSW tSA ADDRESS DATAOUT An 1 Latency tHW tHA An+1 tCD2 Qn tCKLZ OE tOE Notes: 31. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge. 32. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH. 33. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock. 34. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK. Numbers are for reference only. An+2 tDC Qn+1 tOHZ An+3 Qn+2 tOLZ Document #: 38-06077 Rev. *C Page 15 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Switching Waveforms (continued) Bank Select Read[35, 36] tCH2 CLK tSA ADDRESS(B1) tSC CE(B1) tCD2 DATAOUT(B1) tSA ADDRESS(B2) A0 tHA A1 tSC CE(B2) tSC DATAOUT(B2) tCKLZ tHC tCD2 Q2 tCKLZ tCKHZ tCD2 Q4 tSC Q0 tDC A2 tHC tHC tCD2 Q1 tDC A3 A4 tCKLZ A5 tCKHZ tCD2 Q3 tCKHZ A0 tHC tHA A1 A2 A3 A4 A5 tCYC2 tCL2 Read-to-Write-to-Read (OE = tCH2 CLK LOW)[34, 37, 38, 39, 40] tCL2 tCYC2 CE tSC tHC tSW R/W tSW ADDRESS tSA DATAIN DATAOUT READ An tHA tCD2 Qn tDC tHW An+1 An+2 tHW An+2 An+2 tSD tHD Dn+2 An+3 tCKHZ NO OPERATION WRITE Notes: 35. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 36. ADS = CNTEN= BE0 - BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH. 37. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 38. During "No Operation," data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. 39. CE0 = OE = BE0 - BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 40. CE0 = BE0 - BE1 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK. Document #: 38-06077 Rev. *C Page 16 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Switching Waveforms (continued) Read-to-Write-to-Read (OE Controlled)[34, 37, 39, 40] tCH2 CLK tCYC2 tCL2 CE tSC tHC tSW tHW R/W tSW An tHW An+1 tHA An+2 tSD tHD Dn+2 tCD2 Dn+3 tCD2 Qn tOHZ Qn+4 An+3 An+4 An+5 ADDRESS tSA DATAIN DATAOUT OE READ WRITE READ Read with Address Counter tCH2 CLK tSA ADDRESS tSAD ADS An Advance[39] tCYC2 tCL2 tHA tHAD tSAD CNTEN tSCN DATAOUT Qx-1 READ EXTERNAL ADDRESS tHCN Qx tDC READ WITH COUNTER tCD2 Qn tSCN Qn+1 tHAD tHCN Qn+2 Qn+3 COUNTER HOLD READ WITH COUNTER Document #: 38-06077 Rev. *C Page 17 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Switching Waveforms (continued) Write with Address Counter Advance [40] tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2 INTERNAL ADDRESS tSAD ADS tHAD An An+1 An+2 An+3 An+4 CNTEN tSCN DATAIN tSD Dn tHD WRITE EXTERNAL ADDRESS tHCN Dn+1 WRITE WITH COUNTER Dn+1 Dn+2 Dn+3 Dn+4 WRITE COUNTER HOLD WRITE WITH COUNTER Document #: 38-06077 Rev. *C Page 18 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Switching Waveforms (continued) Counter Reset[41, 42] tCYC2 tCH2 tCL2 CLK tSA ADDRESS INTERNAL ADDRESS An tHA Am Ap Ax tSW tHW 0 1 An Am Ap R/W ADS CNTEN tSRST tHRST CNTRST tSD DATAIN tHD D0 tCD2 Q0 tCKLZ READ ADDRESS 0 tCD2 Q1 Qn [43] DATAOUT COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 1 READ ADDRESS An READ ADDRESS Am Notes: 41. CE0 = BE0 - BE1 = LOW; CE1 = MRST = CNT/MSK = HIGH. 42. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. 43. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document #: 38-06077 Rev. *C Page 19 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Switching Waveforms (continued) Readback State of Address Counter or Mask Register[44, 45, 46, 47] tCYC2 tCH2 tCL2 CLK tSA tHA EXTERNAL ADDRESS A0-A16 INTERNAL ADDRESS tSAD tHAD ADS tSCN tHCN CNTEN tCD2 DATAOUT Qx-2 Qx-1 tCKHZ Qn tCKLZ Qn+1 Qn+2 Qn+3 An tCA2 or tCM2 An* An An+1 An+2 An+3 An+4 LOAD EXTERNAL ADDRESS READBACK COUNTER INTERNAL ADDRESS INCREMENT Notes: 44. CE0 = OE = BE0 - BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 45. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle. 46. Address in input mode. Host can drive address bus after tCKHZ. 47. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document #: 38-06077 Rev. *C Page 20 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Switching Waveforms (continued) Left_Port (L_Port) Write to Right_Port (R_Port) Read[48, 49, 50] tCH2 CLKL tSA L_PORT ADDRESS tSW R/WL tCKHZ tSD Dn tCCS An tHW tHA tCYC2 tCL2 tHD L_PORT DATAIN tCYC2 tCL2 tCH2 tCKLZ CLKR tSA R_PORT ADDRESS An tHA R/WR tCD2 R_PORT DATAOUT tDC Qn Notes: 48. CE0 = OE = ADS = CNTEN = BE0 - BE1 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 49. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data will be Read out. 50. If tCCS < minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock. Document #: 38-06077 Rev. *C Page 21 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Switching Waveforms (continued) Counter Interrupt and Retransmit[16, 43, 51, 52, 53, 54] tCH2 CLK tCYC2 tCL2 tSCM tHCM CNT/MSK ADS CNTEN COUNTER INTERNAL ADDRESS 3FFFC 3FFFD 3FFFE tSCINT 3FFFF tRCINT Last_Loaded Last_Loaded +1 CNTINT Notes: 51. CE0 = OE = BE0 - BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 52. CNTINT is always driven. 53. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 54. The mask register assumed to have the value of 3FFFFh. Document #: 38-06077 Rev. *C Page 22 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Switching Waveforms (continued) MailBox Interrupt Timing[55, 56, 57, 58, 59] tCH2 CLKL tSA L_PORT ADDRESS INTR tCYC2 tCL2 tHA An tSINT tRINT An+1 An+2 An+3 tCYC2 tCL2 7FFFF tCH2 CLKR tSA R_PORT ADDRESS Am tHA Am+1 7FFFF Am+3 Am+4 Table 7. Read/Write and Enable Operation (Any Port)[1, 18, 60, 61, 62] Inputs OE X X X L H X CLK CE0 H X L L L CE1 X L H H H R/W X X L H X Outputs DQ0 - DQ17 High-Z High-Z DIN DOUT High-Z Deselected Deselected Write Read Outputs Disabled Operation Notes: 55. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 56. Address "7FFFF" is the mailbox location for R_Port of the 9Mb device. 57. L_Port is configured for Write operation, and R_Port is configured for Read operation. 58. At least one byte enable (BE0 - BE1) is required to be active during interrupt operations. 59. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock. 60. OE is an asynchronous input signal. 61. When CE changes state, deselection and Read happen after one cycle of latency. 62. CE0 = OE = LOW; CE1 = R/W = HIGH. Document #: 38-06077 Rev. *C Page 23 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Ordering Information 512K x 18 (9Mb) 3.3V Synchronous CYD09S18V Dual-Port SRAM Speed (MHz) 133 100 Ordering Code CYD09S18V-133BBC CYD09S18V-100BBC CYD09S18V-100BBI Speed (MHz) 167 133 Package Name BB256 BB256 BB256 Package Name BB256 BB256 BB256 Package Name BB256 BB256 BB256 Package Name BB256 BB256 BB256 Package Type Operating Range 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (BGA) Commercial 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (BGA) Commercial 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (BGA) Industrial Operating Range 256K x 18 (4Mb) 3.3V Synchronous CYD04S36V Dual-Port SRAM Ordering Code CYD04S18V-167BBC CYD04S18V-133BBC CYD04S18V-133BBI Speed (MHz) 167 133 Package Type 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (BGA) Commercial 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (BGA) Commercial 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (BGA) Industrial Operating Range 128K x 18 (2Mb) 3.3V Synchronous CYD02S18V Dual-Port SRAM Ordering Code CYD02S18V-167BBC CYD02S18V-133BBC CYD02S18V-133BBI Speed (MHz) 167 133 Package Type 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (BGA) Commercial 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (BGA) Commercial 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (BGA) Industrial Operating Range 64K x 18 (1Mb) 3.3V Synchronous CYD01S18V Dual-Port SRAM Ordering Code CYD01S18V-167BBC CYD01S18V-133BBC CYD01S18V-133BBI Package Type 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (BGA) Commercial 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (BGA) Commercial 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (BGA) Industrial Document #: 38-06077 Rev. *C Page 24 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Package Diagram 256-Ball FBGA (17 x 17 mm) BB256 TOP VIEW O0.05 M C O0.25 M C A B O0.450.05(256X)-CPLD DEVICES (37K & 39K) PIN 1 CORNER 1 A B C 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BOTTOM VIEW PIN 1 CORNER 9 8 7 6 5 4 3 2 1 A B C O0.50 (256X)-ALL OTHER DEVICES 16 15 14 13 12 11 10 +0.10 -0.05 1.00 D E F G D E F G 17.000.10 15.00 H J K L H J K L N P R T 7.50 M M N P R T 1.00 B 0.700.05 7.50 0.15 C 15.00 A A SEATING PLANE A1 +0.10 -0.05 0.25 C 17.000.10 0.20(4X) C REFERENCE JEDEC MO-192 A1 0.36 0.56 A 1.40 MAX. 1.70 MAX. 0.35 51-85108-*F FLEx18 and FLEx18-E are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-06077 Rev. *C Page 25 of 26 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Document History Page Document Title: CYD01S18V/CYD02S18V/CYD04S18V/CYD09S18V FLEx18TM 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM Document Number: 38-06077 REV. ** *A ECN NO. 259671 289711 Issue Date See ECN See ECN Orig. of Change WWZ YDT New data sheet Change Pinout D10 from NC to VSS Changed tRSCNTINT to tRSINT Added tRSINT to the master reset timing diagram Added ISB5 and changed IIX2 Change Pinout C10 from REVR[2,4] to NC[2,5] Change Pinout G5 from VDDIOL to REVL[2,3] Added note for VCORE Removed preliminary status Description of Change *B *C 327354 365320 See ECN See ECN AEQ YDT Document #: 38-06077 Rev. *C Page 26 of 26 |
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